The present invention relates to phase comparators and clock recovery circuits, and more particularly, to techniques of phase comparison and clock recovery for data signals with high-speed bit rates using a simple phase comparison system.
High-speed serial data transferring such as typified by IEEE (Institute of Electrical and Electronics Engineers) 1394b requires that the receiving side should reproduce a clock signal in accordance with the frequency and phase of a data signal from the sending side. For this operation, a clock recovery circuit is indispensable. One type of the architecture for such a clock recovery circuit is a simple phase comparison system that performs serial processing.
The simple phase comparison system is such that a data signal is input into a reference input of a PLL (Phase Locked Loop), and an input voltage to a voltage controlled oscillator (VCO) is controlled to match the phases of the data signal and a clock signal that has been fed back. This system has a simple configuration and a small-scale circuit area, which are very advantageous in cases in which the number of channels is large. However, the whole circuit needs to operate at the frequency of the bit rate of the data signal, and therefore, it is necessary to provide a phase comparator capable of high-speed operation.
FIG. 15 shows a circuit diagram of a conventional phase comparator. The conventional phase comparator comprises a phase comparator section 100 and a window generator section 1000.
The window generator section 1000 receives as input a signal INDATA and a comparison completion signal NR_WINDOW, and turns a comparison window signal NEN_PD to “L” according to the change of the signal INDATA when the comparison completion signal NR_WINDOW is at “H”. The window generator section 1000 can operate in such a manner that the comparison window signal NEN_PD changes when a signal NPD given from a power down terminal is at “H”.
The phase comparator section 100 receives the comparison window signal NEN_PD as input, and detects the phase difference (performs a phase comparison) between a data signal DATA_PD and a clock signal CLK_PD. The phase comparator section 100 is activated because the comparison window signal NEN_PD has changed to “L”, and performs a phase comparison. As the result of the phase comparison, it outputs a signal UP and a signal DN. The phase difference is represented as the difference in the pulse widths between the signal UP and the signal DN. Upon completion of the phase comparison, the phase comparator section 100 turns the comparison completion signal NR_WINDOW to “L”.
Next, the operation of the conventional phase comparator is described referring to the timing chart of FIG. 16. It is assumed here that the signal NPD is at “H”.
At time t1, a rise of the signal INDATA occurs. In response to this, the window generator section 1000 turns the comparison window signal NEN_PD to “L” at time t2, on the condition that the comparison completion signal NR_WINDOW is at “H”. The phase comparator section 100 is activated because the comparison window signal NEN_PD has changed to “L”, and it detects a rise of the data signal DATA_PD at time t3 and outputs the signal UP at time t4. It also detects a rise of the clock signal CLK_PD at time t4 and outputs the signal DN at time t5.
Upon completion of the phase comparison, the phase comparator section 100 turns the comparison completion signal NR_WINDOW to “L” at time t6. Because the comparison completion signal NR_WINDOW becomes “L”, the window generator section 1000 turns the comparison window signal NEN_PD to “H” at time t7. Because the comparison window signal NEN_PD becomes “H”, the phase comparator section 100 is inactivated, thus stopping outputting of the signals UP and DN. As a result of this, the comparison completion signal NR_WINDOW becomes “H” at time t8. Then, at time t9, the next rise of the signal INDATA occurs, and thereafter, the same processing as described above is repeated.
The conventional phase comparator performs all the processes, which are the activation of the phase comparator section 100, the phase comparison, the transfer of the comparison completion signal NR_WINDOW to the window generator section 1000, and the inactivation of the phase comparator section 100, within one cycle period of the data signal. When the bit rate of the data signal is at low speed, it is possible to sequentially perform the phase comparison, as described above. However, when the bit rate is at high speed and in the order of one gigabit per second, the above-described phase comparison can cause problems.
The time required for the phase comparison fluctuates according to power supply voltages, temperatures, process conditions, and the like. Because of this, under certain conditions, there are cases that not all the above-described processes concerning the phase comparison can be completed within one cycle period of the data signal. If such cases arise, signal racing takes place between the signal INDATA indicating the timing of the phase comparison and the comparison completion signal NR_WINDOW, causing the phase comparator to operate abnormally.